The present invention relates to computer simulation of electronic circuitry and, in particular, to a method and apparatus for synchronizing multiple, concurrently executing tests of a simulation of complex circuitry.
In designing complex circuitry such as application-specific integrated circuits (xe2x80x9cASICsxe2x80x9d) or circuitry which includes several ASICs, the designed logic of such circuitry is typically simulated in a computer using data and computer programs to thereby test the viability and accurate performance of the designed logic. By doing so, design flaws can be detected prior to expending the engineering and financial resources and time required to physically build the circuitry. To simulate circuitry using data and computer programs, the circuitry is described in a hardware description language (xe2x80x9cHDLxe2x80x9d) to form a model. One example of an HDL is the Verilog HDL processed by the Cadence Verilog hardware simulator available from Cadence Design Systems, Inc. of San Jose, Calif. The HDL model of a circuit typically includes a description of components of the state of the circuit and a description of the behavior of the circuit. The behavior of the circuit generally includes inter-relationships between various components of the state of the circuit.
A hardware simulator then uses the HDL model of the circuitry to simulate the circuitry. The hardware simulator is a computer process which accepts data defining simulated signals to be placed on certain parts of the simulated circuit and then changes the state of the circuit in accordance with the simulated signals. The certain parts of the circuit include, for example, terminals, lines, or registers of the simulated circuit.
Circuitry which is simulated in this manner is becoming increasingly complex; therefore, simulation of such circuitry on a single computer processor is becoming less feasible. Specifically, simulations of particularly complex circuits require intolerable amounts of time and computer resources to execute. The Interface Application describes a mechanism by which a complex circuit is divided into multiple circuit parts and by which the circuit parts are simulated by individual simulation models which can execute on multiple constituent computers of a computer network.
In addition, the mechanism described in the Interface Application permits multiple tests of the simulated circuit to execute concurrently. A test of a simulated circuit is a series of computer instructions and data which collectively define simulated signals to be placed at particular locations within the simulated circuit and simulated signals to be sampled at other particular locations within the simulated circuit. For example, a test can include computer instructions which direct (i) that a specific simulated signal is stored within a specific register of the simulated circuit, (ii) that the circuit is simulated for a number of cycles of a simulated clock signal, and (iii) that a resulting simulated signal is retrieved from a second register of the simulated circuit.
It is important that a simulation of a circuit has a quality which is generally known as repeatability. Repeatability of a test or of a combination of tests refers to consistency in the results of such tests in multiple executions of such test or combination of tests without changes in the design of the simulated circuit or the simulated signals to be applied to the simulated circuit. Without repeatability, tracking the execution of the one or more tests and the various circuit parts of the simulated circuit to analyze the tests and/or the simulated circuit to detect design errors becomes extremely difficult and complex.
When simulating a circuit according to multiple, concurrently executing tests, it is possible that the particular order in which transactions between the tests and the simulated circuit are initiated vary from one execution of the simulation of the circuit to another execution. Such is possible since the multiple tests execute concurrently and can execute on different computers of a computer network. Thus, whether a first of the tests or a second of the tests initiates a transaction with the simulated circuit before the other can vary from simulation to simulation and can depend, for example, on the relative processing speeds of the respective computers within which the first and second tests execute. As used herein, a transaction is an operation in which data representing simulated signals are written to or read from a particular component of the state of the simulated circuit. Examples of transactions include simulating data writes and/or reads to registers of the simulated circuit and driving simulated signals on or sampling simulated signals from a bus of the simulated circuit.
Thus, to ensure repeatability, the order in which transactions are initiated must be consistent from one simulation of the simulated circuit to another. What is therefore needed is a mechanism by which transactions between multiple, concurrently executing tests and a simulated circuit are synchronized.
In accordance with the present invention, the synchronization state of each test which interacts with a circuit simulation is represented and controlled by a respective local synchronization thread (xe2x80x9cLSTxe2x80x9d) of a hub through which each test interacts with each circuit simulation. When in a synchronization state in which a test is permitted to interact with a particular circuit simulation, the LST corresponding to the test prevents the circuit simulation from advancing simulated time by acquisition by the LST of a hold lock on the circuit simulation. The LST releases the hold lock when the synchronization state of the test is a state in which the test cannot interact with the circuit simulation.
Each test is permitted to interact with the circuit simulation in a particular state. When each test completes interaction with the circuit simulation, each test enters a barrier mechanism. The barrier mechanism is used to ensure that all tests which are to request reservations of devices of the circuit simulation have requested from the hub such reservations before any test proceeds. In this way, the hub can establish the order in which such requests are granted in a repeatable manner as described more completely in the Reservation Application. As each test enters the barrier mechanism, execution of the test is suspended and a reference to the test is added to a thread list. When all tests which are to enter the barrier have done so, each thread identified by a reference on the thread list is awakened and execution of the test resumes. Thus, in accordance with the present invention, repeatability of each simulation is ensured.